By Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier
Analog Circuit layout comprises the contribution of 18 tutorials of the seventeenth workshop on Advances in Analog Circuit layout. each one half discusses a particular to-date subject on new and necessary layout rules within the quarter of analog circuit layout. every one half is gifted via six specialists in that box and state-of-the-art info is shared and overviewed. This booklet is quantity 17 during this profitable sequence of Analog Circuit layout.
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Additional resources for Analog Circuit Design - High-Speed Clock And Data Recovery, High-Performance Amplifiers, Power Management
M. Meghelli, S. , “A 10 Gb/s 5-Tap-DFE-4-Tap-FFE transceiver in 90 nm CMOS”, ISSCC Dig. of Tech. Papers, pp. 80–81, Feb. 2006. 4. K. J. Wong, C. K. Yang, “A Serial-Link Transceiver with Transition Equalization”, ISSCC Dig. of Tech. Papers, pp. 82–83, Feb. 2006. 5. Fibre Channel, “Physical Interface-4 (FC-PI-4)”, Int. Committee for Information Technology Standardization (INCITS), Rev. 7, Sept. 2007. 6. R. Kajley, P. Hurst, “A Mixed-Signal Decision-Feedback Equalizer That Uses a Look-Ahead Architecture”, IEEE J.
Unfortunately, the bang-bang detector leads to highly nonlinear behavior for the CDR since it can distinguish only the sign of the phase error, and not its magnitude. Since a consistent jitter transfer function implies linear dynamics, the bang-bang phase detector will not be suitable for high performance CDR applications such as SONET. One possible way of linearizing the bang-bang detector is to add extra levels to it as shown in Fig. 5. In this case, the magnitude of the phase error can be sensed in addition to its sign, though only in discrete intervals which are set by the delay of the buffers shown in the figure.
Committee for Information Technology Standardization (INCITS), Rev. 7, Sept. 2007. 6. R. Kajley, P. Hurst, “A Mixed-Signal Decision-Feedback Equalizer That Uses a Look-Ahead Architecture”, IEEE J. Solid-State Circuits, Vol. 32, No. 3, March 1997. 7. S. Gondi, B. Razavi, “Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers”, IEEE J. Solid-State Circuits, Vol. 42, No. 9, September 2007. 8. M. Harwood, N. 5 Gb/s SerDes in 65 nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery”, ISSCC Dig.