By Jose Moreira
Supplying a whole advent to the state of the art in high-speed electronic trying out with computerized attempt gear (ATE), this sensible source is the 1st ebook to concentration solely in this more and more vital subject. that includes transparent examples, this one-stop reference covers all serious facets of the topic, from high-speed electronic fundamentals, ATE instrumentation for electronic functions, and attempt and measurements, to creation trying out, help instrumentation and textual content fixture layout.
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Additional info for An Engineer's Guide to Automated Testing of High-Speed Interfaces
4 Jitter Jitter and jitter testing are very important but sometimes complex subjects. There exists a myriad of resources spread through different books, articles, and applications notes. Some of the available references on this topic include [1, 2, 11–14]. This section addresses some of the important points regarding jitter in high-speed digital interfaces. ” A significant instant for a digital signal can be defined as the rising or falling edge from a bit transition crossing a voltage threshold level.
In this case the jitter value is measured by looking at the variation of the adjacent periods in regard to the expected clock period. For clock signals it is also typical to define the maximum deviation of each single period of the clock signal under measurement from that of the ideal clock as the period jitter . 22 Cycle-to-cycle jitter definition. 1 Jitter Histogram The jitter histogram is one of the most commonly used ways of analyzing the jitter of a digital signal. The idea is to measure the time interval error of each edge of the signal and generate a histogram of the measurements.
Embedded Clock Interfaces Embedded clock interfaces combine the clock information and the data content within the same signal. On the receiver side, a so-called clock data recovery (CDR) circuit separates the clock and data information from this signal and reconstructs the data content. The benefit of combining the data and clock phase information on the same signal is that both are affected equally by signal disturbances. This allows embedded clock interfaces to transmit data at very high data rates on a PCB.