By Larry M. Hyman
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42 Logic Designer's Handbook CMOS outputs with no load have virtually no offset voltage from y DD or 0 V, but are output-current dependent. A load drawing, say, 1 m A will degrade the output by 1 volt because of the inherent IK on-resistance of the η and ρ channel FETs. This effect is particularly important when mixing CMOS with other logic families or with discrete components. B Ν 03 N I Ü4 Vss Fig. 2 . 1 4 C M O S N A N D gate. It is a simple matter to construct other logic gates with CMOS. In fig.
The gate thus has the truth table: Β A Ζ 0 0 1 1 0 1 0 1 1 1 1 0 which is the truth table for a NAND gate. The output transistors Q 3 , Q4 are known as a t o t e m pole o u t p u t , and have several advantages over the simple pull-up resistor of fig. 2. With the DTL gate of fig. 2, R3 has to be kept low to reduce RC time constants with stray and line capacitance. When the gate output is 0, Q l is turned on and R l passes a relatively high current. The gate power consumption is therefore significantly higher in the 0 output state than in the 1 output state which can cause power supply noise.
12b operates with the drain connection negative with respect to the source, and can again be considered as a simple switch. When the gate is negative with respect to the source, the switch is closed; when V Q § is zero the switch is open. Logic Families 41 It is possible to construct a logic family solely from η channel or ρ channel FETs, but virtually all MOS logic uses both (hence the name CMOS). A typical CMOS inverter is shown in fig. 13. When the input is at a 1, Q l is turned off and Q2 is turned on (by the rules of fig.